RISC-v on ZC706 Evaluation Board - Part IV: petalinux

 One year ago (Dec 2022) I made two posts to try modelling RISC-v on ZC706:

• RISC-v on ZC706 Evaluation Board - Part II
• RISC-v on ZC706 Evaluation Board - Part I

Then later in this April I post RISC-v on ZC706 Evaluation Board - Part III to dive into generating FPGA bit stream with Vivado 2016.2. It is a bit success, but eventually still running into issue: "./fesvr-zynq pk hello" still get "ERROR: No cores found". As mentioned in the old post, likely that I need to setup PetaLinux. After several busy months, now I get some spare time to tackle this.

fesvr-zynq probably was built from rocket-chip/riscv-tools/riscv-fesvr, but per https://github.com/ucb-bar/fpga-zynq/issues/87, the issue likely is not coming from this binary:

zhemao commented Jul 9, 2018

Sorry, I forgot to update all the binaries in the uramdisk.image.gz.

Could you please try the files in the master branch of fpga-images-zedboard? I've tested them on my board and they seem to work. https://github.com/ucb-bar/fpga-images-zedboard.

But likely https://github.com/ucb-bar/fpga-images-zc706 not updated. So likely what I need is using PetaLinux tools to build this uramdisk.image.gz for fpga-images-zc706.

Since I haven't been touching the zc706 board for a while, also it is now connected to a new Linux host, let me refresh the whole thing for reproducing the problem. With zc706 UART connected to Linux, once power up the board, kernel log shows:

 usb 2-10: new high-speed USB device number 7 using xhci_hcd
 usb 2-10: New USB device found, idVendor=0403, idProduct=6014, bcdDevice= 9.00
 usb 2-10: New USB device strings: Mfr=1, Product=2, SerialNumber=3
 usb 2-10: Product: Digilent USB Device
 usb 2-10: Manufacturer: Digilent
 usb 2-10: SerialNumber: 210251842966
 ftdi_sio 2-10:1.0: FTDI USB Serial Device converter detected
 usb 2-10: Detected FT232H
 usb 2-10: FTDI USB Serial Device converter now attached to ttyUSB0

This ttyUSB0 likely is the Jtag. Per host kernel log ([    5.208150] usb 4-4: cp210x converter now attached to ttyUSB1), the Uart over USB device ttyUSB1 is there no matter the zc706 board is powered on or off. To connect to the Uart, would need terminal like putty(needs XServer) or minicom(runs in shell). I take minicom as I'm connecting the host with ssh. Run: sudo minicom -s to setup serial port.

Once connected, it would prompt zynq login, use root/root which is default credential. If Ethernet cable is connected, then can use ssh to login the board, the default IP is 192.168.1.5 (refer to the fpga-zynq project page).

With the h/w environment ready, now let's start the PetaLinux adventure.

I have downloaded PetaLinux Tools Installer and ZC706 BSP from Xilinx site several months back. The site also provides common images for Embedded Vitis Platforms. And per note:The ‘common image’ packages contain a prebuilt Linux kernel and root file system that can be used with any Zynq™, Zynq™ MP or Versal board for embedded Vitis platform developers. These files need to be copied to an SD flash card along with the platform specific boot image (boot.bin) available from the Vitis™ Embedded Platform page. Also included is the ‘sysroot’ required for embedded Vitis platform application development. The sdk.sh script must to be used to setup the compressed Yocto Project SDK on a Linux development host properly...PetaLinux Tools installation is not necessary to use the common images. Licenses and sources used to create the common image content is provided. This is a bit confusing. Which do we really need? Regarding Vivado v.s. Vitis, Digilent has a page of explanation: Fundamentally, the differences are down to the perspective of the developer using the tool. Vivado offers a hardware-centric approach to designing hardware, while Vitis offers a software-centric approach to developing *both* hardware and software. Sounds like we don't need Vitis stuff? 

To start the journey, I'm following UG1144 - PetaLinux Tools Documentation Reference Guide.

To setup working environment, run:

source <path-to-installed-PetaLinux>/settings.sh

To use PetaLinux SDK, run:

source <path-to-installed-PetaLinux>/components/yocto/buildtools/environment-setup-x86_64-petalinux-linux

The first is creating PetaLinux project with zc706 BSP:

petalinux-create -t project -s <path-to-bsp>

As the user guide said, using -p to specify the platform architecture, such as '-p arm' for Zynq and '-p aarch64' for Zynq UltraScale+ MPSoC, may save a little disk space. Also tftp server is preferred, Without a TFTP service, you cannot download Linux system images to the target system using the U-Boot network/TFTP capabilities. This can be ignored for other boot modes.

The user guide mentioned exporting hardware platform to PetaLinux project, which can be done from Vivado menu File=>Export=>Export Hardware=>choice of 'Pre-synthesis' and 'Include bitstream', no idea, so I selected the 2nd options to include more. This step generates rocketchip_wrapper.xsa file. 

The user guide also mentioned creating project with template, I guess that is for complexity, since I already created project from BSP, I don't see a need of that.

Run 'petalinux-config --get-hw-description ../fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/rocketchip_wrapper.xsa' to launch system config. There is lot of setting, and likely can keep the default setting per the User Guide.

Run 'petalinux-build' to build images and it will take a while (will perform a lot of download as well), with 4232 tasks in my case.

The project folder will hold pre-built image once created, even before performing the build. Description of images can be found from the README under the root of the project. The build will generate new images to images/linux folder, such as: zynq_fsbl.elf, image.ub, zImage, uImage, u-boot.elf,  system.dtb, and rootfs.tar.gz, which might be the replacement of uramdisk.image.gz? The fpga-zynq project  zc706/fpga-images-zc706 contains files as:
boot.bif
boot.bin
devicetree.dtb
uImage
uramdisk.image.gz
boot_image
|-FSBL.elf
|-rocketchip_wrapper.bit
|-u-boot.elf

So the boot_image folder contains FSBL, FPGA bitstream and U-Boot.

The  uramdisk.image.gz seems is not a normal gzip archive as I cannot open it with 7-zip, therefore cannot confirm whether it is rootfs.tar.gz from the build. Following https://xilinx.github.io/Embedded-Design-Tutorials/docs/2022.1/build/html/docs/Introduction/Zynq7000-EDT/4-linux-for-zynq.html, I packed the boot.bin with following:

cd images/linux

petalinux-package --boot --fsbl zynq_fsbl.elf --fpga system.bit --u-boot u-boot.elf

Then copy the generated "BOOT.BIN" to SD card, yes, the name is all in capital.

Some Acronym for PetaLinux:

FSBL: First Stage BootLoader

PMU: Platform Management Unit, manage and perform the multi-staged booting process

TF-A: Trust Firmware-A, a transparent bare-metal application layer executed in Exception Level 3 (EL3) on the APU.

BIF: Bootgen Image Format

APU: Application Processing Unit

RPU: Realtime Processing Unit

MCS: might stand for Intel Micro Computer Set, which is file ext name for Intel Hex (refer to wikipedia)