RISC-v on ZC706 EVB - Part III: build w/ Win11/WSL2/Vivado 2016.2

 Continue my journey with of RISC-v on ZC706 Evaluation Board - Part II. Finally get some spare time can back on this. Since it may need some effort to get PetaLinux setup and debug the executable issue, I changed my focus to setup Vivado 2016.2 on another Windows 11 + WSL2 PC. Luckily Xilinx_Vivado_SDK_2016.2_0605_1.tar.gz is just around 11.1GB, even much smaller than 2016.4 package. And I chose WSL2 as on Windows 11 it support GUI, and would be less hassle do the build under Linux. However, I do run into several problem with fresh installed WSL2:

• Got 'libawt_xawt.so: libXrender.so.1: cannot open shared object file: No such file or directory' when running Vivado xsetup to install Vivado. Search from internet shows I need to do "sudo apt-get install libxrender1" , and that did work. Then hit next issue as below:
• Got 'libawt_xawt.so: libXtst.so.6: cannot open shared object file: No such file or directory', turns out that I need do 'sudo apt install libxtst6'. Then next issue:
• Got 'libawt_xawt.so: libXi.so.6: cannot open shared object file: No such file or directory', need to do "sudo apt install libxi6"

With that, xsetup is up and running. For installing option, I selected Vivado HL Design Edition as the WebPACK one might not have all features I need, and I don't need DSP support (for choices, may refer to Xilinx 2016.4 WebPACK Vivado and SDK Install on Windows 7 SP1 (css-techhelp.com) for more detail). Then the installation stuck with the flash screen for quite long time, which made me doubt whether it hanged or crashed. Luckily, it is not. After a while, the install option diag shows up, and I can select and continue the installation. At beginning I checked the option for creating Desktop shortcut, but not sure where it will go as I don't have Ubuntu Desktop installed. The installation not proceeding after a while, with log file name showed in console. By checking the log, likely there is issue with the shortcut. So re-run the installer, this time, not select the shortcut and create group box, however, installer still hangs, and log file shows it probably is running tcl script for generating the device list:

Executing script Generating installed device list: /home/Suser/Vivado/2016.2/bin/vivado [-nolog, -nojournal, -mode, batch, -source, /home/$user/.xinstall/Vivado_2016.2/scripts/xlpartinfo.tcl, -tclargs, /home/$user/Vivado/2016.2/data/parts/installed_devices.txt]
Tried 'sudo apt install tcl' but doesn't help. If manually run about  line, will get:
application-specific initialization failed: couldn't load file "librdi_commontasks.so": libncurses.so.5: cannot open shared object file: No such file or directory

Per this link, need to do: sudo apt install libncurses5

With that, I successfully installed Vivado 2016.2 under WSL. Then I start to pull fpga-zynq.git and build with it as described in fpga-zynq: 2) Pushing your rocket modifications to the FPGA, steps as:

• Start WSL Ubuntu terminal
  
• git clone https://github.com/ucb-bar/fpga-zynq.git to /mnt/c/workspace which can be easily accessed from Windows
  
• Run sudo apt install openjdk-8-jdk-headless; sudo update-alternatives --install "/usr/bin/java" "java" "/usr/lib/jvm/java-8-openjdk-amd64/bin/java" 1
• There is a strange thing happened. To install JDK8 under WSL, sometime would need to do sudo apt update, but somehow WSL give me an error as: "Release file for http://archive.ubuntu.com/ubuntu/dists/jammy-updates/InRelease is not valid yet (invalid for another 1d 3h 20min 52s). Updates for this repository will not be applied.". https://itsfoss.com/fix-repository-not-valid-yet-error-ubuntu/ gives me a clue on this: my WSL clock is skewed for some reason and it is lagged more than 1 day. So have to issue 'wsl --shutdown' then restart WSL to fix the problem
  
• For fresh WSL, would need do: sudo apt install make
  
• cd to git repo zc706 subfolder, run:
  

  make init-submodules

• Run below command, may get a lot of warn and error related to sbt, probably just ignore them:
  

  make rocket

• If see Cannot run program "dtc", do: sudo apt install device-tree-compiler
• Once 'make rocket' successfully completed, run Vivado setting script in the installation path such as: source ~/Vivado/2016.2/settings64.sh
• run  make project, and soon will see something like 'Wrote  : </mnt/c/code/fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/zc706_rocketchip_ZynqFPGAConfig.srcs/sources_1/bd/system/system.bd>' at the end. 'system.bd' is folder contains system folder.
  
• Now run

  make fpga-images-zc706/boot.bin

  will see output like:

Successfully read diagram <system> from BD file </mnt/c/code/fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/zc706_rocketchip_ZynqFPGAConfig.srcs/sources_1/bd/system/system.bd>

Verilog Output written to : /mnt/c/code/fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/zc706_rocketchip_ZynqFPGAConfig.srcs/sources_1/bd/system/hdl/system.v
Verilog Output written to : /mnt/c/code/fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/zc706_rocketchip_ZynqFPGAConfig.srcs/sources_1/bd/system/hdl/system_wrapper.v
Wrote  : </mnt/c/code/fpga-zynq/zc706/zc706_rocketchip_ZynqFPGAConfig/zc706_rocketchip_ZynqFPGAConfig.srcs/sources_1/bd/system/system.bd>
INFO: [BD 41-1029] Generation completed for the IP Integrator block proc_sys_reset_0 .
WARNING: [xilinx.com:ip:processing_system7:5.5-1] system_processing_system7_0_0: The Zynq BFM requires an AXI BFM license to run. Please ensure that you have purchased and setup the AXI BFM license prior to running simulation with this block. Please contact your Xilinx sales office for more information on purchasing this license
INFO: [BD 41-1029] Generation completed for the IP Integrator block processing_system7_0 

...

Attempting to get a license for feature 'Synthesis' and/or device 'xc7z045'
WARNING: [Common 17-348] Failed to get the license for feature 'Synthesis' and/or device 'xc7z045'
3 Infos, 1 Warnings, 0 Critical Warnings and 1 Errors encountered.
synth_design failed
ERROR: [Common 17-345] A valid license was not found for feature 'Synthesis' and/or device 'xc7z045'. Please run the Vivado License Manager for assistance in determining
which features and devices are licensed for your system.
Resolution: Check the status of your licenses in the Vivado License Manager. For debug help search Xilinx Support for "Licensing FAQ".
INFO: [Common 17-206] Exiting Vivado at Fri Apr  7 19:48:34 2023...
[Fri Apr  7 19:48:34 2023] synth_1 finished
wait_on_run: Time (s): cpu = 00:00:00.15 ; elapsed = 00:00:28 . Memory (MB): peak = 1186.469 ; gain = 0.000 ; free physical = 241 ; free virtual = 1777
# launch_runs impl_1 -to_step write_bitstream
ERROR: [Common 17-70] Application Exception: Failed to launch run 'impl_1' due to failures in the following run(s):
synth_1
These failed run(s) need to be reset prior to launching 'impl_1' again.
...

Likely would need a license to run synth and impl. As mentioned at https://dzone.com/articles/create-a-bootbin-program-an-sd-card-and-boot-a-zc7, The ZC706 has an XC7Z045-2FFG900 C SoC. This chip is not supported in WebPACK (see [link]) like the chip on the ZC702. You can get a 30-day license at [link].

Next, might see 'bootgen: command not found'. This could happen if user didn't run the Xilinx Vivado settings64.sh shell script, or XiLinx SDK wasn't installed. If the SDK is installed, bootgen should be available under Vivado/2016.2/bin folder. Without SDK, make boot.bin would fail. So need to select SDK during installation as below (I only select Zynq-7000 to save space and installing time. Also, not select Acquire or Manage a License Key as I will deal with that separately):

If already have Vivado installed, then it won't allow you to re-install at same location. Would need to launch Vivado, then goto help->Add Design Tools or Devices...->Check SDK and click install.

After all this, finally can successfully build the boot.bin. With this boot.bin copied to SD card, it can successfully boot the PetaLinux (connect the Uart USB, and use root/root to login). But running "./fesvr-zynq pk hello" still get "ERROR: No cores found".

Also tried following the prompted message for the problem 5 mentioned in Risc-v on zc706 evaluation board - Part I: ERROR: [BD_TCL-109] This script was generated using Vivado <2016.2> and is being run in <2022.1> of Vivado. Please run the script in Vivado <2016.2> then open the design in Vivado <2022.1>. Upgrade the design by running "Tools => Report => Report IP Status...", then run write_bd_tcl to create an updated script.

I opened the project file zc706_rocketchip_ZynqFPGAConfig.xpr created by 2016.2 Vivado with 2022.1 Vivado, and keep the project as Read-only while the new version Vivado prompt for choice. It would still treat the board type as error:

• [Board 49-67] The board_part definition was not found for xilinx.com:zc706:part0:1.0. This can happen sometimes when you use custom board part. You can resolve this issue by setting 'board.repoPaths' parameter, pointing to the location of custom board files. Valid board_part values can be retrieved with the 'get_board_parts' Tcl command.

For this, no need to update update zc706/src/tcl/zc706_rocketchip_ZynqFPGAConfig.tcl, but update the project xpr file directly as it is XML format, just update <Option Name="BoardPart" Val="xilinx.com:zc706:part0:1.0"/> to xilinx.com:zc706:part0:1.4. For above update instruction, I cannot find 'write_bd_tcl' script, but did find there is a man doc as Vivado/2022.1/doc/eng/man/write_bd_tcl. And 'Report IP' now is under menu/Report but not Tools. Open the Tcl Console (menu/Window->Tcl Console), issue command write_bd_tcl with output filename. It may prompt:  ERROR: [BD 5-229] Please open or create a block design first. So need to select from left Flow Navigator->IP INTEGRATOR-> Open Block Design before running the write_bd_tcl command.