Program Arty A7 FPGA to be a RISC-V processor - Part I

 This is a note for things encounter while following instruction to program a Digilent Arty A7 board as RISC-V core. As https://digilent.com/reference/programmable-logic/arty-a7/reference-manual described: The Arty A7, formerly known as the Arty, is a ready-to-use development platform designed around the Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx. 

https://digilent.com/reference/programmable-logic/arty-a7/start has tutorials Installing Vivado, Vitis, and Digilent Board Files and Running a RISC-V Processor on the Arty A7. The first link has instruction for how to install software/files for the FPGA development. The second link is for how to program Arty A7 as RISC-v core.

For installing Vivado/Vitis, software package is huge. Xilinx download page recommends to use the web installer. However, people like me was hitting "Peer not authenticated" issue as mentioned here. The solution is download the Xilinx Unified Installer 2022.1 SFD gzip file, extract and install. The gzip file is 73.8G, download and extract would need a lot of hard disk space. At least, it works.

For programming Arty A7 as RISC-V, I'm getting many trouble. First, download SiFive Freedom processor with git command: 

git clone --recursive https://github.com/sifive/freedom.git

this would take quite some time to download the git plus a bunch of sub-modules. And may fail with some sub-modules as there are so many of them, and either there is network issue, or the repo server URL was change. If the clone isn't success, then have to fix that, otherwise, won't be able to build. To sync missing sub-module, refer to Git - Submodules (git-scm.com) May run:

# copy the new URL to your local config
$ git submodule sync --recursive
# update the submodule from the new URL
$ git submodule update --init --recursive

If seeing not empty warning, might need to clean those sub-folder first. Might see different problem like:

• Submodule 'env' (git://github.com/ucb-bar/riscv-test-env.git) registered for path 'rocket-chip/torture/env'

Cloning into '/home/$user/freedom/rocket-chip/torture/env'...
fatal: unable to connect to github.com:
github.com[0: 140.82.114.3]: errno=Connection timed out

cd to freedom/rocket-chip/torture and check the '.gitmodules' would get:

cat .gitmodules
[submodule "env"]
        path = env
        url = git://github.com/ucb-bar/riscv-test-env.git

Per this post, either need to make sure to have SSH key setup, or use https instead of SSH protocol for the git url. So manually run: git clone https://github.com/ucb-bar/riscv-test-env.git env

Or run this to update the .gitmodules file:

sed s#git://github.com#https://github.com#g -i .gitmodules
git submodule sync 

• For problem like: "server certificate verification failed. CAfile: none CRLfile: none", try this as mentioned in this stackoverflow post: sudo apt update ; sudo apt-get install apt-transport-https ca-certificates -y ; sudo update-ca-certificates

Once git sync is OK, the first step is building the toolchain. Change working directory to rocket-chip/riscv-tools, and check README.md there: would need to set RISCV environment variable first, like this:  export RISCV=/mnt/c/develop/riscv, also, several packages are needed for building the toolchain. Run the build.sh script to build, and it will take some time.

Next step is building Verilog installation. Please note the instruction

make -f Makefile.e300artydevkit Verilog

should have the target 'Verilog' as all little case 'verilog' (which is in common.mk). There is several other cases in the Digilent instruction which should use all little case as well, such as Xilinx=>xilinx

< to be continue >