Program Arty A7 FPGA to be a RISC-V processor - Part III

 Since having lot of problem to follow https://digilent.com/reference/programmable-logic/arty-a7/reference-manual instruction on Windows/WSL/Cygwin, so I moved to do that on Linux/Ubuntu. Most thing goes smoothly. Do need to update several .gitmodules file to get everything synced, i.e. replace git://github.com to https://github.com.

When start to build the toolchain, I hit the first problem is while building riscv-openocd:

Multiple definitions of bitbang_swd originating from jtag/drivers/bitbang.h

Per https://github.com/riscv/riscv-openocd/issues/480, this likely is due to newer GCC 10+ which defaulting to -fno-common. I'm using GCC 11.3.0. So just as suggested, add the 'extern' keyword in front of the const swd_driver struct in bitbang.h. 

Then hit this one for compiling riscv-fesvr ../fesvr/dtm.cc:

'runtime_error' is not a member of std 

According to https://github.com/Azure/azure-storage-fuse/issues/421, it may relate to g++ version: According to https://en.cppreference.com/w/cpp/error/runtime_error, the include should not be exception.h but <stdexcept>. So the fix is adding #include <stdexcept> to dtm.cc.

Similar need to be done for riscv-isa-sim/riscv/devices.h.

With that, the toolchain build is OK. And make for verilog is done without any issue. However, when run

make -f Makefile.e300artydevkit mcs

Seeing this: ERROR: [Synth 8-439] module 'BootROM' not found [/path_of_freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.v:242627]

Make -f Makefile.e300artydevkit mcs fails - module BootRom not found · Issue #96 · sifive/freedom · GitHub someone says re-sync repo solved the problem for him. My Vivado is 2022.1 build, and Digilent's instruction is using 2017 build. Hopefully the new version Vivado is not the problem.

By looking into the make log (there is log file under builds folder), the BootROM module is referenced in the .v file, which is coming from the .fir file as 'extmodule BootROM'. So likely a dependency is missing.

Then I went back to check files in the repo, and noticed in the root README.md, it mentioned two things:

• As of March 1 2021, SiFive is archiving the freedom repository. The code here is not being actively maintained, and we can't continue to provide updates while the fpga boards, software ecosystems and other dependencies change.

• Install sbt, varilator (probably typo of verilator) and scala which are required for building from Chisel

Per https://www.chisel-lang.org/: The Constructing Hardware in a Scala Embedded Language (Chisel) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel is powered by FIRRTL (Flexible Intermediate Representation for RTL), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations.

sbt home site: https://www.scala-sbt.org/. Per Wikipedia:

sbt is an open-source build tool for Scala and Java projects, similar to Apache's Maven and Gradle.

And the keyword extmodule is from Chisel. So likely, would need to install them as the README said. The instruction for installing sbt might need to be updated as it doesn't work with new Ubuntu. Refer to https://www.scala-sbt.org/download.html. Not sure why the README.md specified verilator_3_922. Ubuntu has this package, so I run sudo apt install verilator directly, same for scala.

With that, now running make mcs will ask for python. I installed python-is-python3 package, and now seeing a new error, same as described as https://github.com/chipsalliance/rocket-chip/issues/1991:

Traceback (most recent call last):
  File "rocket-chip/scripts/vlsi_rom_gen", line 90, in iterate_by_n
    batch += (next(it),)
StopIteration

As the ticket said, most likely due to I had Python3 but not Python (2.7) installed. Interestingly, the problem is gone after 2nd run of make, and then back to the no BootROM module issue.

Will chasing down the cause. <to be continue>

Program Arty A7 FPGA to be a RISC-V processor - Part II

 When I started on this journey by following instruction from https://digilent.com/reference/programmable-logic/arty-a7/start, I installed Xilinx Vivado on Windows PC as that is the primary working environment. Then when I started building RISC-v, I realized the instruction is all Linux oriented, so I decided to use WSL2 environment to build. The toolchain was successfully built. "make -f Makefile.e300artydevkit verilog" is also OK. But running into problem with "make -f Makefile.e300artydevkit mcs" runs into problem, as it needs to invoke vivado, which I haven't installed, and do not plan to install it under WSL2, simply because it takes too much disk space, and I'm not sure the sure the GUI would work well under WSL2.

Farther looking into the print out from the make mcs output, turns out it is running this from common.mk:

bit := $(BUILD_DIR)/obj/$(MODEL).bit
$(bit): $(romgen) $(f)
        cd $(BUILD_DIR); vivado \
                -nojournal -mode batch \
                -source $(fpga_common_script_dir)/vivado.tcl \
                -tclargs \
                -top-module "$(MODEL)" \
                -F "$(f)" \
                -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
                -board "$(BOARD)"


# Build .mcs
mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
$(mcs): $(bit)
        cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
So it is possible to utilize the Vivado Windows installation, either still do the make under WSL2, or run the make with GNU shell under Windows (such as Cygwin). 

Approach A: Run make under WSL2, install missing Vivado Linux executable

For Windows Vivado installation, it also include Linux vivado shell script under the bin folder. So would need to add the path to the bin like below:

export PATH=$PATH:/mnt/c/Xilinx/Vivado/2022.1/bin

However, Windows Vivado installation won't have Linux executable installed. Would see error like:

WARNING: /mnt/c/Xilinx/Vivado/2022.1/tps/lnx64/jre11.0.11_9 does not exist.
ERROR: Could not find 64-bit executable.
ERROR: /mnt/c/Xilinx/Vivado/2022.1/bin/unwrapped/lnx64.o/vivado does not exist
So would need to extract these missing binaries from installation package.

Approach B: Run make using Cygwin

My freedom.git was synced to my WSL2 home folder. So first thing is find out the Windows path to it. Information can be found from https://superuser.com/questions/1185033/what-is-the-home-directory-on-windows-subsystem-for-linux. For my WSL2 installed on Windows 11, under %LOCALAPPDATA%\Packages\Packages\CanonicalGroupLimited.UbuntuonWindows_79rhkp1fndgsc\LocalState is only a 'ext4.vhdx' file, which likely is a virtual disk file. So the way to access it from Cygwin would be map it as a driver, with command like this: net use U: \\wsl.localhost\Ubuntu

Then from Cygwin, cd U: should change CWD to the root dir of WSL2 Ubuntu. However, the make command might still fail with error like this:

Sourcing tcl script 'C:/Users/$win_user/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
source /cygdrive/u/home/$wsl_user/freedom/fpga-shells/xilinx/common/tcl/vivado.tcl
couldn't read file "/cygdrive/u/home/$wsl_user/freedom/fpga-shells/xilinx/common/tcl/vivado.tcl": no such file or directory

To get around this, I moved the freedom folder to be under /mnt/c, which is the Windows C: drive. And this time, it gave me a new error when running make under Cygwin:

Cannot find a jar file even the file exist. So for now, give up on this, until later have some time. Probably can do that directly from Vivado?

<to be continue: moving to do that on Linux>