Program Arty A7 FPGA to be a RISC-V processor - Part III

 Since having lot of problem to follow https://digilent.com/reference/programmable-logic/arty-a7/reference-manual instruction on Windows/WSL/Cygwin, so I moved to do that on Linux/Ubuntu. Most thing goes smoothly. Do need to update several .gitmodules file to get everything synced, i.e. replace git://github.com to https://github.com.

When start to build the toolchain, I hit the first problem is while building riscv-openocd:

Multiple definitions of bitbang_swd originating from jtag/drivers/bitbang.h

Per https://github.com/riscv/riscv-openocd/issues/480, this likely is due to newer GCC 10+ which defaulting to -fno-common. I'm using GCC 11.3.0. So just as suggested, add the 'extern' keyword in front of the const swd_driver struct in bitbang.h. 

Then hit this one for compiling riscv-fesvr ../fesvr/dtm.cc:

'runtime_error' is not a member of std 

According to https://github.com/Azure/azure-storage-fuse/issues/421, it may relate to g++ version: According to https://en.cppreference.com/w/cpp/error/runtime_error, the include should not be exception.h but <stdexcept>. So the fix is adding #include <stdexcept> to dtm.cc.

Similar need to be done for riscv-isa-sim/riscv/devices.h.

With that, the toolchain build is OK. And make for verilog is done without any issue. However, when run

make -f Makefile.e300artydevkit mcs

Seeing this: ERROR: [Synth 8-439] module 'BootROM' not found [/path_of_freedom/builds/e300artydevkit/sifive.freedom.everywhere.e300artydevkit.E300ArtyDevKitConfig.v:242627]

Make -f Makefile.e300artydevkit mcs fails - module BootRom not found · Issue #96 · sifive/freedom · GitHub someone says re-sync repo solved the problem for him. My Vivado is 2022.1 build, and Digilent's instruction is using 2017 build. Hopefully the new version Vivado is not the problem.

By looking into the make log (there is log file under builds folder), the BootROM module is referenced in the .v file, which is coming from the .fir file as 'extmodule BootROM'. So likely a dependency is missing.

Then I went back to check files in the repo, and noticed in the root README.md, it mentioned two things:

• As of March 1 2021, SiFive is archiving the freedom repository. The code here is not being actively maintained, and we can't continue to provide updates while the fpga boards, software ecosystems and other dependencies change.

• Install sbt, varilator (probably typo of verilator) and scala which are required for building from Chisel

Per https://www.chisel-lang.org/: The Constructing Hardware in a Scala Embedded Language (Chisel) is an open-source hardware description language (HDL) used to describe digital electronics and circuits at the register-transfer level that facilitates advanced circuit generation and design reuse for both ASIC and FPGA digital logic designs. Chisel is powered by FIRRTL (Flexible Intermediate Representation for RTL), a hardware compiler framework that performs optimizations of Chisel-generated circuits and supports custom user-defined circuit transformations.

sbt home site: https://www.scala-sbt.org/. Per Wikipedia:

sbt is an open-source build tool for Scala and Java projects, similar to Apache's Maven and Gradle.

And the keyword extmodule is from Chisel. So likely, would need to install them as the README said. The instruction for installing sbt might need to be updated as it doesn't work with new Ubuntu. Refer to https://www.scala-sbt.org/download.html. Not sure why the README.md specified verilator_3_922. Ubuntu has this package, so I run sudo apt install verilator directly, same for scala.

With that, now running make mcs will ask for python. I installed python-is-python3 package, and now seeing a new error, same as described as https://github.com/chipsalliance/rocket-chip/issues/1991:

Traceback (most recent call last):
  File "rocket-chip/scripts/vlsi_rom_gen", line 90, in iterate_by_n
    batch += (next(it),)
StopIteration

As the ticket said, most likely due to I had Python3 but not Python (2.7) installed. Interestingly, the problem is gone after 2nd run of make, and then back to the no BootROM module issue.

Will chasing down the cause. <to be continue>

Program Arty A7 FPGA to be a RISC-V processor - Part II

 When I started on this journey by following instruction from https://digilent.com/reference/programmable-logic/arty-a7/start, I installed Xilinx Vivado on Windows PC as that is the primary working environment. Then when I started building RISC-v, I realized the instruction is all Linux oriented, so I decided to use WSL2 environment to build. The toolchain was successfully built. "make -f Makefile.e300artydevkit verilog" is also OK. But running into problem with "make -f Makefile.e300artydevkit mcs" runs into problem, as it needs to invoke vivado, which I haven't installed, and do not plan to install it under WSL2, simply because it takes too much disk space, and I'm not sure the sure the GUI would work well under WSL2.

Farther looking into the print out from the make mcs output, turns out it is running this from common.mk:

bit := $(BUILD_DIR)/obj/$(MODEL).bit
$(bit): $(romgen) $(f)
        cd $(BUILD_DIR); vivado \
                -nojournal -mode batch \
                -source $(fpga_common_script_dir)/vivado.tcl \
                -tclargs \
                -top-module "$(MODEL)" \
                -F "$(f)" \
                -ip-vivado-tcls "$(shell find '$(BUILD_DIR)' -name '*.vivado.tcl')" \
                -board "$(BOARD)"


# Build .mcs
mcs := $(BUILD_DIR)/obj/$(MODEL).mcs
$(mcs): $(bit)
        cd $(BUILD_DIR); vivado -nojournal -mode batch -source $(fpga_common_script_dir)/write_cfgmem.tcl -tclargs $(BOARD) $@ $<
So it is possible to utilize the Vivado Windows installation, either still do the make under WSL2, or run the make with GNU shell under Windows (such as Cygwin). 

Approach A: Run make under WSL2, install missing Vivado Linux executable

For Windows Vivado installation, it also include Linux vivado shell script under the bin folder. So would need to add the path to the bin like below:

export PATH=$PATH:/mnt/c/Xilinx/Vivado/2022.1/bin

However, Windows Vivado installation won't have Linux executable installed. Would see error like:

WARNING: /mnt/c/Xilinx/Vivado/2022.1/tps/lnx64/jre11.0.11_9 does not exist.
ERROR: Could not find 64-bit executable.
ERROR: /mnt/c/Xilinx/Vivado/2022.1/bin/unwrapped/lnx64.o/vivado does not exist
So would need to extract these missing binaries from installation package.

Approach B: Run make using Cygwin

My freedom.git was synced to my WSL2 home folder. So first thing is find out the Windows path to it. Information can be found from https://superuser.com/questions/1185033/what-is-the-home-directory-on-windows-subsystem-for-linux. For my WSL2 installed on Windows 11, under %LOCALAPPDATA%\Packages\Packages\CanonicalGroupLimited.UbuntuonWindows_79rhkp1fndgsc\LocalState is only a 'ext4.vhdx' file, which likely is a virtual disk file. So the way to access it from Cygwin would be map it as a driver, with command like this: net use U: \\wsl.localhost\Ubuntu

Then from Cygwin, cd U: should change CWD to the root dir of WSL2 Ubuntu. However, the make command might still fail with error like this:

Sourcing tcl script 'C:/Users/$win_user/AppData/Roaming/Xilinx/Vivado/Vivado_init.tcl'
source /cygdrive/u/home/$wsl_user/freedom/fpga-shells/xilinx/common/tcl/vivado.tcl
couldn't read file "/cygdrive/u/home/$wsl_user/freedom/fpga-shells/xilinx/common/tcl/vivado.tcl": no such file or directory

To get around this, I moved the freedom folder to be under /mnt/c, which is the Windows C: drive. And this time, it gave me a new error when running make under Cygwin:

Cannot find a jar file even the file exist. So for now, give up on this, until later have some time. Probably can do that directly from Vivado?

<to be continue: moving to do that on Linux>
 

Program Arty A7 FPGA to be a RISC-V processor - Part I

 This is a note for things encounter while following instruction to program a Digilent Arty A7 board as RISC-V core. As https://digilent.com/reference/programmable-logic/arty-a7/reference-manual described: The Arty A7, formerly known as the Arty, is a ready-to-use development platform designed around the Artix-7™ Field Programmable Gate Array (FPGA) from Xilinx. 

https://digilent.com/reference/programmable-logic/arty-a7/start has tutorials Installing Vivado, Vitis, and Digilent Board Files and Running a RISC-V Processor on the Arty A7. The first link has instruction for how to install software/files for the FPGA development. The second link is for how to program Arty A7 as RISC-v core.

For installing Vivado/Vitis, software package is huge. Xilinx download page recommends to use the web installer. However, people like me was hitting "Peer not authenticated" issue as mentioned here. The solution is download the Xilinx Unified Installer 2022.1 SFD gzip file, extract and install. The gzip file is 73.8G, download and extract would need a lot of hard disk space. At least, it works.

For programming Arty A7 as RISC-V, I'm getting many trouble. First, download SiFive Freedom processor with git command: 

git clone --recursive https://github.com/sifive/freedom.git

this would take quite some time to download the git plus a bunch of sub-modules. And may fail with some sub-modules as there are so many of them, and either there is network issue, or the repo server URL was change. If the clone isn't success, then have to fix that, otherwise, won't be able to build. To sync missing sub-module, refer to Git - Submodules (git-scm.com) May run:

# copy the new URL to your local config
$ git submodule sync --recursive
# update the submodule from the new URL
$ git submodule update --init --recursive

If seeing not empty warning, might need to clean those sub-folder first. Might see different problem like:

• Submodule 'env' (git://github.com/ucb-bar/riscv-test-env.git) registered for path 'rocket-chip/torture/env'

Cloning into '/home/$user/freedom/rocket-chip/torture/env'...
fatal: unable to connect to github.com:
github.com[0: 140.82.114.3]: errno=Connection timed out

cd to freedom/rocket-chip/torture and check the '.gitmodules' would get:

cat .gitmodules
[submodule "env"]
        path = env
        url = git://github.com/ucb-bar/riscv-test-env.git

Per this post, either need to make sure to have SSH key setup, or use https instead of SSH protocol for the git url. So manually run: git clone https://github.com/ucb-bar/riscv-test-env.git env

Or run this to update the .gitmodules file:

sed s#git://github.com#https://github.com#g -i .gitmodules
git submodule sync 

• For problem like: "server certificate verification failed. CAfile: none CRLfile: none", try this as mentioned in this stackoverflow post: sudo apt update ; sudo apt-get install apt-transport-https ca-certificates -y ; sudo update-ca-certificates

Once git sync is OK, the first step is building the toolchain. Change working directory to rocket-chip/riscv-tools, and check README.md there: would need to set RISCV environment variable first, like this:  export RISCV=/mnt/c/develop/riscv, also, several packages are needed for building the toolchain. Run the build.sh script to build, and it will take some time.

Next step is building Verilog installation. Please note the instruction

make -f Makefile.e300artydevkit Verilog

should have the target 'Verilog' as all little case 'verilog' (which is in common.mk). There is several other cases in the Digilent instruction which should use all little case as well, such as Xilinx=>xilinx

< to be continue >

Install multiple Ubuntu instances in WSL2

 Yes, there are probably many post about this, such as https://cloudbytes.dev/snippets/how-to-install-multiple-instances-of-ubuntu-in-wsl2 and https://stackoverflow.com/questions/51584765/how-do-you-install-multiple-separate-instances-of-ubuntu-in-wsl. Still want to make this post about a special case not covered anywhere else.

Run wsl -l can show all installed distribution.

If want to remove one of the distribution, run: wsl --unregister <DistributionName>

Recently I'm playing with ROS Kinetic. Unfortunately, as mentioned http://wiki.ros.org/kinetic/Installation/Ubuntu, only old Wily (15.10) and Xenial (16.04 LTS) are supported. It's possible to get it setup with VirtualBox or VMware VM, but I'd like to go with WSL2 on Windows 11, as mentioned in my the other post, it is possible to enable Ubuntu GUI with the Windows 11 build 22000+. One problem here is the Xenial Ubuntu is no longer available from Microsoft Store, so would need to use WSL2 very useful 'import' feature. For this, would need a tar.gz file of the Ubuntu distribution, the ISO image file doesn't work with WSL import. Another problem now, seems there is no tar for the Xenial Desktop image, but the base image is available such as the amd64 one as ubuntu-base-16.04.6-base-amd64.tar.gz, and it is pretty small, just 41MB. Using command like this to import it:

wsl --import xenial c:\Users\%USERNAME%\wsl_xenial .\Downloads\ubuntu-base-16.04.6-base-amd64.tar.gz 

(Note: for imported distro, if run wsl --unregister, it will delete distro file). There is no Ubuntu desktop and only user root is created. To add new user, run following command with the root account to add the user and add it to sudo group:

adduser newuser

usermod -aG sudo newuser

Try this to verify the user group and switch to it:

groups newuser

su - newuser 

Type 'exit' to switch back to root, and run 'apt update' and 'apt install sudo', so later the new user can do apt install with sudo command. This is the minimum for installing other package as new user. 

To get the desktop environment, run: 'sudo apt install ubuntu-desktop', which installs most common packages. On WSL/Windows OS side, need to follow https://learn.microsoft.com/en-us/windows/wsl/tutorials/gui-apps, installing the AMD/nVidia/Intel's Virtual GPU (vGPU) driver first, then run: 'wsl --update' and 'wsl --shutdown' for a clean restart. May install gedit and run it to verify the GUI. Per my testing, with Ubuntu 20.04 LTS the GUI works fine. However, doesn't work for Ubuntu 16.04 Xenial, seeing segment fault and probably core dump. Tried Diagnosing "cannot open display" type issues with WSLg but not much luck. So leave it aside for now.

我的小鸡们

 六月18日星期周六，对我们全家来说是悲伤的一天，来到我们家十一天的小芦花鸡大毛不幸在我们的后院失踪了，而且最可能是被鹰之类的飞禽捉走了。本来它们是在纸箱里，上面盖着。因为味有点大，太太把纸箱放后院deck上。风大把盖子吹掉了，小鸡就自己跑了出来，可我们不知道，不然一定会看着它们的，因为以前就有小鹰虎视眈眈的站fence上看我们的小鸟。
六月7日，两只小芦花鸡刚刚落户我们家，大概有一周多大，浑身黄白棕黄色的毛，一只颈背棕色毛多的，我们给它取名一撮毛，另一只颈两侧各有些棕毛，我们叫它俩撮毛，后来就简称大毛二毛。大毛二毛很招人喜爱，总是小声小气的鸡鸡个不停，甚至在边吃饭睡觉时也会唧唧，即像在呼唤同伴，又像在表达很好很舒服很好吃。失去了大毛，让我想起了鲁迅《祝福》里的祥林嫂，好在很快，我们又收养了新的小鸡，给了我们一些抚慰。
失去大毛那天，太太带着孩子去买回两只新小鸡，它们是那么小，恐怕刚出生一两天而已，刚来时，站着就要睡着了，也不大吃东西，好像不知道怎么吃。我们叫它俩团团和圆圆，寄予小鸡一家团圆。为了不再老让孩子们想起大毛伤心，我们叫二毛为芦花。

团团圆圆一来就把芦花当作妈妈，总往芦花的翅膀和肚子下钻。好在芦花很nice,从开始觉得很wierd，到后来就顺其自然，带着两个小妹妹吃饭睡觉草地里跑来跑去。鸡食很让我们发愁，不知道它们爱吃什么，于是给它们吃麦片燕麦片，玉米面拌菜，还有苍蝇。天好时我们经常在后院坐板凳上，地上铺着小鸡pupu的报纸，举着苍蝇拍打苍蝇。小鸡们知道啪一声响就有好吃的，所以经常等在身旁，甚至迫不及待的自己追苍蝇，当然总是一无所获。它们快乐的长大着。为了区分两只小的，我们在圆圆小鸡翅膀上mark黑颜色，就叫它小黑。后来我们又从别人那买回一只毛黑一点的小鸡，主人说5月底买的，叫Fluffy,可个头比芦花还小，它以前常被同养的两只小鸭子欺负，胆子很小，好在很快就和芦花团团圆圆和睦相处,我叫它毛毛。它也很快学会吃苍蝇。六月28日周二，我因有事去了办公室，不幸happens again:太太把小鸡放在纸箱里，然后放deck上。为了透气，我在纸箱上给大毛二毛开了些小窗口，可团团圆圆小，可以从窗口跑出来，太太从后院进屋，随手关拉门，没想到从纸箱外逃出来的小圆圆跟在后面，被挤，不幸。为了不让Emily伤心，我急忙从办公室赶回，几经周折，去卖鸡家又买了个小鸡，找不到大一点的，新小鸡叫声响亮，可不大会吃，总想睡觉。因太小，没法骗小孩，只好说farmer要求把小圆圆换走了。这个小家伙，我叫它球球，因为它跑起来像个滚动的棉花球。它长的好像很慢，都过了一个多星期，它还和刚来时差不多大。它睡觉喜欢钻到芦花的翅膀或肚子下，有时芦花已经趴下，小球球会跳到芦花背上，一旦芦花站起来，小球就有机会钻了。

上周日(Jul 3），太太又从别人那买回两只小鸡，有大毛二毛来时大。这样我们就有6只小鸡了。
芦花很喜欢在后院跑，每次它都是最难捉回来的。它甚至听得懂它的名字，每次听到我们喊芦花，就知道有苍蝇吃了，会从院子的不知那个角落连跑带飞的奔到我们打苍蝇的地方来。后来可能因小鸡太多了，小的小鸡时常在我们身旁等苍蝇吃，芦花再从远处赶来常吃不到，它就不大理会名字被叫到了。芦花很早就学会玩土洗澡了，有时就趴在我们种的西红柿旁的土地里，享受泥土和阳光浴。除了苍蝇，芦花和小鸡们很喜欢吃面条，也喜欢米饭。看小鸡们抢食物吃有时很好笑，小的小鸡抢到好吃的会飞快的在其它鸡面前钻来转去。芦花看着很大，可前几天我们给它称了，却还不到一磅。芦花不在外边跑时很乖，轻轻push它，它就肯安静地趴在我们的手和胳膊上。我们都在想芦花再大一点，就会给我们下蛋了。
8日周五早，Rogers的cell phone和无线网同时down了。今天,六只小鸡一早就又被放出来，吃了些菜拌玉米面，喝了些水，在后院撒欢。突然芦花有些异样，站在草地里不动，我以为它在pupu，果然它拉了一点黑稀东西，可还是很不舒服，没过多久它就开始趴下了，连我走过去摸它，它也没再像以前那样run away。我抚摸了它，没多久它变得更加痛苦，头颈开始使劲扭动，很吓人，又让我们手足无措，不知怎样才能帮它，Rogers的网络还没回来，电话是好了，可我们都不知打给谁。我只能帮它按摩腹部，有那么一刻，芦花又站起来，跑开了，让我以为一切转危为安了，可没多久芦花又趴下了。眼睛也不愿睁开了。生命在慢慢逝去。在最后的一刻里，芦花再次从我的手足挣扎出去，跑到了它心爱的西红柿旁的土地里。我把它再次抱回手里没多久，它终于解脱了，安详的躺在我的胳膊上。

我们把它埋在香椿树和桑树下，离小圆圆埋葬的地方很近，希望它在天堂与一撮毛还有小圆圆团聚。
生命有时是如此的脆弱，我们在不知不觉中付出了关爱，在那一刻被残忍的剥夺了。在我们眼前耳边缠绕着它们的身影和声音，我们恐怕不再有勇气去收养新的小鸡。
愿小芦花安息